A typical image sensor senses light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After the integration cycle is completed, charge is converted into a voltage that is supplied to the output terminals of the device. The charge to voltage conversion is accomplished either directly in the sensor pixels, such as in the Active Pixel CMOS image sensors, or remotely off the sensing area in charge conversion amplifiers. In the remote conversion process, charge must be transported to the sensing amplifier by a well know charge transferring process using various vertical and horizontal Charge Coupled Device (CCD) registers.
U.S. Pat. No. 5,337,340 teaches the basic concept of charge carrier multiplication that can be used in a typical CCD register. The multiplication is based on a single carrier impact ionization that is induced by the application of suitable clocking voltages to the various device gates. The suitable clocking voltages generate high fields in the structure, and when a carrier is injected into these high field regions, it gains energy and may cause impact ionization. This process thus increases the original number of carriers that arrive at the charge detection amplifier. This is a desirable effect, since the carrier multiplication that is based on single carrier impact ionization is almost noiseless. It is much easier to detect many electrons per single received photon than a single electron by the current state of the art charge detection amplifiers. The noise floor of the present day charge conversion amplifiers is approximately 10 electrons, and cannot be easily reduced.
The charge multiplication, however, presents a problem for the design of the CCD registers. As the number of transported carriers gradually increases, larger and larger wells have to be used. This may not be easily accomplished in the registers that are restricted in both dimensions by the sensor pixel size. Examples are the vertical registers in Frame Transfer (FT) sensors, Time Delay Integrate (TDI) sensors, or Interline Transfer (IT) sensors. It is thus desirable to incorporate most of the charge multiplication function into the horizontal CCD registers whose width is restricted in only one dimension.
A second problem resulting from the charge multiplication is related to the DR of the charge conversion structures at the input of the charge detection amplifiers.
Typically, charge is transferred on a suitable charge detection node whose capacitance converts arrived charge into an increment of voltage. It is desirable to have a high sensitivity and low noise for the charge conversion. This dictates a very small value for the node capacitance. However, when charge is multiplied, the voltage increment may be so large that the detection node cannot handle it. The available maximum voltage swing thus undesirably limits the DR of the sensor. To avoid these problems it is therefore advantageous to compress the DR directly in the charge domain before charge conversion into a voltage and at the same time eliminate the need for the gradual size increase of the register wells.
Hynecek presents one possible solution to these problems in a [provisional] patent application [60/200,255]. As shown in FIG. 1, the CCD area image sensor 100 has an image sensing area 101 and an extended serial register 102 connected to the charge multiplication region of variable width 103. A charge overflow region 104 then supplies charge into at least two outputs 105 and 106 with a different conversion gain that are finally combined into one output 107. The resulting device has a piece-wise linear transfer characteristic, which accomplishes DR compression and avoids saturation of the output charge detection nodes. While this solution is useful it has drawbacks of consuming larger chip area, the piece wise transfer characteristic has a limited range of usefulness, and combining the outputs together after charge has been converted into a voltage increases noise.
It is the purpose of this invention to teach how to overcome limitations of the prior art, and how to achieve high DR readout capability with low noise. The prior art does not show in detail how to incorporate the charge multiplier into a serial register and combine it with the DR compression in each cell to avoid the need for the gradual register well size increase and the saturation of the output charge detection node. The prior art also does not teach how to design the DR compression structure that has, instead of the piece-wise linear characteristic, a superior logarithmic nonlinear transfer characteristic.